---
title: Swiss Startup Chipmind Unveils RTL Canvas for AI Chip Design Review
description: Zurich startup Chipmind's RTL Canvas turns AI-generated chip design changes into visual diffs engineers can review and approve. Early-access pilot now open.
author: Darie Nani (Editor-in-Chief)
date: 2026-07-14T11:17:39.472Z
updated: 2026-07-14T11:36:49.364Z
canonical: https://www.sovereignmagazine.com/article/chipmind-rtl-canvas-ai-chip-design
image: https://cdn.nanimediahouse.com/chipmind-rtl-canvas.webp
categories: Startups
content_type: Spotlight
region: Zurich
publication: Sovereign Magazine
about:
  - type: Organization
    name: Chipmind
    description: Zurich-based semiconductor design startup applying AI agents to chip design and verification. Founded by ETH Zurich PhDs Harald Kröll and Sandro Belfanti, it came out of stealth in October 2025 with $2.5 million in pre-seed funding led by Founderful.
    url: https://www.chipmind.ai
    industry: Semiconductors
    sameAs:
      - https://www.linkedin.com/company/chipmind
      - https://www.crunchbase.com/organization/chipmind
      - https://github.com/chipmind
---

AI agents can now write chip design code faster than human engineers can check it. Chipmind, a Zurich-based semiconductor design startup, has launched RTL Canvas, a tool that turns an AI agent's design changes into diagrams engineers can review, rather than lines of code to be read one at a time.

Engineers using the tool can draw an intended change directly onto a diagram of the chip, and when the agent responds, its edits come back the same way: as a visual overlay on the existing architecture, not a block of text.

## What Is Register Transfer Level Design

Register-transfer level, or RTL, is the blueprint stage of chip design. Before any physical layout exists, engineers describe what data moves between a chip's storage elements, called registers, and what logic transforms it along the way. That description is written in a hardware description language, usually Verilog or VHDL, and functions as the chip's source code: detailed enough to simulate and test, abstract enough for a human to reason about.

RTL sits in the middle of the design flow. Above it are the architectural decisions about what the chip should do; below it, synthesis tools translate the RTL into the logic gates and physical layout sent for fabrication. It is the layer AI agents now write, and the layer where a mistake is cheapest to catch: an error found in RTL costs a rewrite and a fresh simulation, while one that survives into manufactured silicon can force a re-spin of the whole chip. RTL Canvas is Chipmind's attempt to make reviewing that layer visual instead of textual.

## What Chipmind's RTL Canvas Means for Chip Design Engineers

The canvas sits alongside a standard AI chat panel and renders the chip's architecture as an interactive diagram. Chipmind describes it as generative: rather than showing a fixed schematic, the canvas assembles a custom visual interface on the fly, tailored to the task the engineer is working on. When an agent proposes a change, newly added logic appears in green, removed logic in red, and unchanged code is greyed out so engineers can focus on what actually moved.

Before any of that reaches the underlying code, engineers can test changes in a staging sandbox: dragging signals across hierarchies and clock domains, rerouting buses, and prototyping design variations while the design repository itself stays untouched. Chipmind says constraints can be checked visually on the canvas before the agent writes a line of permanent code; only once a change is approved is it synchronised with the underlying hardware description code. Interactive zooming lets an engineer move from a full chip layout down into a single sub-block, with the canvas generating a more detailed view of that section in real time.

The company frames the canvas as the contract between engineer and agent: intent is stated on it, and every change is judged against it. Chipmind calls it the industry's first bidirectional contract surface between engineers and AI agents, arguing that nothing should merge into a design that a human has not understood, and says the approach cuts onboarding times on complex legacy chip designs and reduces the backlog of text-based pull requests that agent-written code creates. An early-access pilot is now open to engineers.

"Engineers don't think in code. They think in blocks and buses. So we built a canvas that shows your existing chip design architecture, and you draw your intended changes right onto it while the AI writes the RTL. And it works both ways: when the AI writes, its changes come back as a visual diff, not a wall of text," said Harald Kröll, CEO and co-founder of Chipmind.

"The core technical breakthrough here is that we've given our AI agents the power to shape the user experience dynamically, while maintaining adherence to the underlying hardware reality," said Dr Sandro Belfanti, CTO and co-founder of Chipmind.

Kröll and Belfanti met during PhD studies at ETH Zurich and have between them worked on more than twenty chips, from mobile-phone modems to systems-on-chip. Chipmind came out of stealth in October 2025 with $2.5 million in pre-seed funding led by Founderful and semiconductor-industry angels. Its first product, Chipmind Agents, applies AI to chip design and verification tasks and is trained on each customer's own design data; the company says it can save engineers up to 40 per cent of their time on repetitive tasks.

## Semiconductor Startups Take on Chip Verification's Bottleneck

Industry surveys put verification at roughly 60 to 70 per cent of the chip design cycle, with the Wilson Research Group estimating that debugging alone consumes about 44 per cent of verification time. Data reported by Semiconductor Engineering shows first-time silicon success rates falling from around 30 per cent historically to 14 per cent in 2024 and 2025, with 70 per cent of re-spins traced to design errors.

Deloitte estimates the semiconductor industry will need roughly one million additional skilled workers globally by 2030, and that the United States alone could be short about 23,000 chip designers by then.

Synopsys, Cadence and Siemens EDA dominate the [EDA tools market](https://www.sovereignmagazine.com/article/why-software-controls-could-reshape-the-global-chip-industry) and each runs an AI-driven design programme; Synopsys launched Synopsys.ai Copilot in 2023 for RTL generation and testbench creation. Those tools increase the volume of machine-written RTL a human still has to review, and Chipmind is pitching RTL Canvas as the review layer for that output. California-based ChipAgents is attacking the same bottleneck with AI agents for chip design and verification.

Chipmind has argued since February, when it said [Europe's €43 billion Chips Act was solving the wrong problem](https://www.sovereignmagazine.com/article/swiss-startup-chipmind-says-europe-s-43bn-chip-bet-missed-the-point), that design productivity rather than fabrication capacity constrains chip output. RTL Canvas applies that argument to the newest constraint, the human review of machine-written designs. The act it criticised aims to lift Europe's share of global chip production from under 10 per cent to 20 per cent by 2030.

## FAQ

**Q: What is RTL in chip design?**
RTL, or register-transfer level, is the blueprint stage of chip design, where engineers describe what data moves between a chip's storage elements and what happens to it, written in a hardware description language before any physical layout exists.

**Q: Why is chip verification such a bottleneck?**
Industry surveys put verification at roughly 60 to 70 per cent of the total chip design cycle, and data reported by Semiconductor Engineering shows first-time silicon success rates falling from around 30 per cent historically to 14 per cent in 2024 and 2025.

**Q: Who are the big EDA vendors building AI chip design tools?**
Synopsys, Cadence and Siemens EDA dominate the electronic design automation market and each runs its own AI-driven design programme; Synopsys launched its Synopsys.ai Copilot for RTL generation and testbench creation in 2023.

**Q: Why is there a shortage of chip design engineers?**
Deloitte estimates the semiconductor industry will need about one million additional skilled workers globally by 2030, with the United States alone facing a shortfall of roughly 23,000 chip designers.

**About Chipmind**

Zurich-based semiconductor design startup applying AI agents to chip design and verification. Founded by ETH Zurich PhDs Harald Kröll and Sandro Belfanti, it came out of stealth in October 2025 with $2.5 million in pre-seed funding led by Founderful.

[Website](https://www.chipmind.ai)